Referring to FIG. 1, as is well-known in the art, Complementary Metal Oxide Semiconductor (CMOS) circuits consist of N-channel and P-channel MOS transistors formed in separate N and P wells 102 on a surface 104 a semiconductor substrate 106. MOS transistors use a gate to control the underlying surface channel 108 joining a source and a drain (not shown in this figure). The channel 108, source and drain are located in the well 102, with the source and drain being doped oppositely to the channel and the well. The circuit may further include a number of isolation features 110, such as shallow trenches filled with a dielectric or field oxide, to electrically isolate devices formed within the well.
The N and P wells 102 are typically formed by axially implanting ions 112 of the appropriate species at high energies in to the surface 104 of the substrate 106 in a region surrounded or defined by a thick (>1 μm thick) photoresist (PR) mask 116. The channels 108 are typically formed by implanting the surface 104 at a low energy. The dose or concentration of dopants implanted into the channel 108 generally determines the threshold voltage (VT) of the finished device. The VT is the minimum gate voltage required to turn on or induce conductance in the channel 108 of the device. For enhancement-mode devices, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel.
Although the above approach has worked well in the past, as device geometries scale, problems such as “well boundary proximity effects” are encountered. Referring to FIG. 1, well boundary proximity effects occur, for example, when ions 112a are scattered from the edge of PR mask 116 during well implantation rather than being blocked or trapped as desired, thereby raising or increasing the concentration of dopant in the channel region of devices near the well boundary. Although this increase in the concentration of dopants has substantially no impact on the operation of devices having relatively large channel width (W) and the devices located far from the well boundary, it becomes significant as channel widths and the well-to-well spacing are reduced into the deep sub-micron range. A graph illustrating the impact of a well boundary effect on VT as a function of channel width (W) is shown in FIG. 2. The top graph, labeled 202, illustrates the effect on devices near the well boundary. The lower graph, labeled 204, illustrates the effect on devices distant from the well boundary. Referring to FIG. 2, the cumulative effect of this added doping coupled with that of the conventional channel implant is to raise the VT of devices formed near the drawn well boundary as channel width (W) decreases. In the example, shown it is seen that VT has been shifted by about 60 mV for a narrow channel device near the drawn well boundary.
Various methods for controlling or compensating for VT variation through design and processing techniques are known in the prior art.
One prior art technique or method requires designers to take variations in VT due to the Well boundary proximity effects into account during the design stage using a physical layout of the circuit and a series of complex modeling equations. That is the variation in VT due to the Well boundary proximity effects are estimated using modeling equations, and the modified accordingly to allow for these variations.
It will be appreciated that this approach is not wholly satisfactory for a number of reasons including the complexity of the model from which the designers must work. Also, there is the added cost and time arising from the need for multiple iterations in designing a circuit, since each change in the circuit layout would typically result in a change in VTs of the devices.
Another technique, not shown, involves an additional compensating threshold adjust implant of all or part of the channel performed just before forming the gate to adjust the doping concentration in the channel region near the well boundary. However, this approach undesirably requires additional photolithography and/or implant steps, and compensation may degrade device performance.
Accordingly, there is a need for a method of controlling VT in MOS devices near the drawn well boundary through the elimination of a well boundary proximity effect. There is a further need for a method of independently adjusting the VT's of specific narrow channel transistors to enhance circuit performance. It is desirable that these methods do not require additional photolithography and/or implant steps. It is still further desirable that the methods are substantially immune to mask misalignment in the well and channel implant steps.
The present invention provides a solution to these and other problems, and offers further advantages over conventional methods of designing and fabricating CMOS devices and circuits.